MOS integrated counter circuit diagram and working principle detailed analysis

The binary flip-flop circuit in the previous section inputs a set of "0" and "1" pulses, that is, the output is reversed only after one bit of input pulse is input. Therefore, an output that repeats 1/2 input cycle can be obtained. MOS integrated counter circuit diagram. Therefore, when these flip-flop circuits are cascaded, a binary counting circuit can be formed, which has binary coding rights of 20, 21, 22, ... 2n from the primary stage. Assuming that the frequency of the input pulse is fi and the number of cascaded stages is n, the repetition frequency of the output pulse of the last stage is

In order to obtain any n-ary counting circuit, feedback can be added to the previous stage. When connected into an n-stage counting circuit, when feedback is added from the n-th stage to the i-th stage, the circuit is equivalent to a 2n~(2i-1)-stage counting circuit.

The MOS integrated circuits drawn into the block diagram of Figure 3.40 and the equivalent circuit diagram of Figure 3.41 are decimal and hexadecimal counters. The circuit consists of a four-level binary flip-flop and a control gate. If the feedback terminal (F) is grounded, it is a hexadecimal binary counter; if the feedback terminal (F) is connected to the output terminal F4, it is a decimal counter.

First, use Figure 3.41 to illustrate the working principle of the first-level binary flip-flop circuit. For ease of description, the high level is regarded as "0" and the low level is regarded as "1". MOS integrated counter circuit diagram. Q3, Q4, Q5, Q6 and its external resistor R2 and Q10, Q11, Q12, Q13, Q14 constitute flip-flop circuits (F/F) 1 and (F/F) 2 respectively. Q1, Q2 constitute an inverter that provides an inverted signal for the input signal, and Q16, Q17, Q18, Q19, and Q20 constitute a reset circuit and a decimal feedback circuit. As a starting condition, now set (F/F)1 and (F/F)2 to remain in the "0" state. It is also assumed that the reset terminal R is open, and the feedback terminal F is connected to the output terminal F4.

In the reset state, since the output of F1~F4 is "0", Q16 is off, Q19 is on, and Q20 is off, so there is no need to consider.

Suppose the end point A and end point B of (F/F) 2 are at "0" and "1", respectively, Q7 on the (F/F1) path is off, and Q8 is on. For this reason, Q3 of (F/F) 1 is in the cut-off state, Q4 is in the on state, and the output terminal F1 is kept in the "0" state.

Here, if the input is "1", Q15 is turned on and Q9 is turned off, forming a feedback circuit from (F/F)1 to (F/F)2. As a result, the "0" signal output by F1 is transmitted to the gate of Q10, Q10 changes from on to off, terminal A changes from "0" to "1", and terminal B changes from "1" to "0". If the input is "0", then Q9 turns on and Q15 turns off, forming a feedback circuit from (F/F) 2 to (F/F) 1.

Because the end point A is "1". So Q7 is turned on, the gate of Q4 is grounded through Q7 and Q9, (F/F)1 is flipped, and the output of F1 changes from "0" to "1". Afterwards, the same action will be repeated every time the input pulse is applied. MOS integrated counter circuit diagram. The second-level binary flip-flop operates exactly the same as the foregoing except that it operates according to the output signal of the first-level F1 and its flipped output signal.

Suppose the input pulse is ten count pulses. Because F2 and F4 are in the "1" state at the same time, Q16 and Q17 are turned on. As a result, Q19 changes from on to off, Q20 and the reset transistors of each stage are turned on, and the output terminal F1 ~F4 becomes "0" and is reset. Thus, the decimal time chart shown in Figure 3.42 can be obtained.

As in the above situation, if the feedback terminal F is connected to F1, it constitutes a ternary counter; the feedback terminal is connected to F3 to constitute a hexadecimal counter.

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