CMOS process p-well and n-well surface structure process introduction

(1) p-well and n-well (p-Well and n-Well)

The design of MOS integrated circuits mainly includes three aspects.

1. Circuit design; 2. Layout design; 3. The relationship between MOS process parameters and circuit parameters.

Therefore, in order to design a MOS integrated circuit with excellent performance, in addition to circuit design, it is necessary to understand the influence of MOS process parameters on circuit performance and master some rules of layout design. This chapter introduces the main processes in MOS integrated circuits-CMOS process and CMOS circuit layout design rules, but for more detailed content in this respect, please refer to the relevant information.

The CMOS circuit is composed of two types of MOS field effect transistors, p-channel and n-channel. We can fabricate p-channel MOS field effect transistors on an n-type silicon wafer substrate, and implant boron ions on the n-type substrate to form a p-well, and fabricate n-channel MOS field effect transistors in the p-well , As shown in Figure 4.1-1a. Similarly, we can also fabricate n-channel MOS field effect transistors on p-type silicon wafer substrates, and implant phosphorus on the p-type substrate to form an n-well, and fabricate p-channel MOS transistors in the n-well , As shown in Figure 4.1-1b. In the figure, G is the gate of the MOS tube, S is the source, D is the drain, and B is the substrate.

In the p-well structure, the n-type silicon substrate is connected to the highest potential type silicon site, and the well is connected to the lowest potential. In the n-well structure, the p-type silicon substrate is connected to the lowest potential and the well is connected to the highest potential. Therefore, between the well and the substrate A reverse pn junction bias voltage is formed, and the well is naturally isolated from the substrate.

The p-well process is developed from the PMOS process, because they are all n-type silicon wafer substrates, and a small number of n-channel MOS devices are made in the well. CMOS process p-well and n-well. It happens that n-channel MOS devices require a higher substrate concentration to obtain a positive threshold voltage, that is, to obtain an enhanced n-channel MOS tube, and the concentration of the P-well must be higher than that of the n-type substrate. Therefore, the p-well process is used a lot in production.

With the development of NMOS technology, many large-scale integrated circuits, such as memory, are made of NMOS technology, because the electron mobility in NMOS field effect transistors is more than twice that of hole mobility in PMOS field effect transistors. . Even CMOS circuits are composed of a large number of NMOS field effect transistors, and only a small number of PMOS devices exist in the peripheral input and output parts. Therefore, it becomes very advantageous to fabricate a large number of NMOS field effect transistors on a p-type substrate, and fabricate the smallest PMOS field effect transistors in an n-well.

In some linear circuits, it is necessary to short-circuit the substrate of the p-channel device with the source to reduce the increase in threshold voltage caused by the reverse bias of the substrate. In this case, using the n-well process, the device that requires the substrate and the source to be shorted is made in a separate n-well. As long as the potential of the n-well is higher than that of the p-type substrate, the well can still be isolated from the substrate. of.

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